EP4CE30F29C7N Datasheet, PDF (83/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
5–21
Figure 5–10 shows a simplified block diagram of the major components of the PLL of
Cyclone IV E devices.
Figure 5–10. Cyclone IV E PLL Block Diagram ⁽¹⁾
Clock inputs ⁴
from pins
GCLK (3)
inclk0
Clock
Switchover
inclk1 _Block
lock
LOCK
circuit
÷n
PFD
clkswitch
clkbad0
clkbad1
activeclock
CP
LF VCO ⁸ ÷2 (2)
8
VCO
Range
Detector
VCOOVRR
VCOUNDR
÷C0
÷C1
÷C2
PLL
output
÷C3 mux
÷C4
GCLKs
External clock output
pfdena
÷M
no compensation;
ZDB mode
source-synchronous;
normal mode
GCLK networks
Notes to Figure 5–10:
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
1 The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the f_VCO specification specified in the Cyclone IV Device Datasheet chapter.
External Clock Outputs
Each PLL of Cyclone IV devices supports one single-ended clock output or one
differential clock output. Only the C0 output counter can feed the dedicated external
clock outputs, as shown in Figure 5–11, without going through the GCLK. Other
output counters can feed other I/O pins through the GCLK.
October 2012 Altera Corporation
Cyclone IV Device Handbook,
Volume 1