EP4CE30F29C7N Datasheet, PDF (337/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
1–57
Fast Recovery from P0s State
The PCIe protocol defines fast training sequences for bit and byte synchronization to
transition from L0s to L0 (PIPE P0s to P0) power states. The PHY must acquire bit and
byte synchronization when transitioning from L0s to L0 state between 16 ns to 4 µs.
Each Cyclone IV GX receiver channel has built-in fast recovery circuit that allows the
receiver to meet the requirement when enabled.
Electrical Idle Inference
In PIPE mode, the Cyclone IV GX transceiver supports inferring the electrical idle
condition at each receiver instead of detecting the electrical idle condition using
analog circuitry, as defined in the version 2.0 of PCIe Base Specification. The inference
is supported using rx_elecidleinfersel[2..0] port, with valid driven values as
listed in Table 1–17 in each link training and status state machine substate.
Table 1–17. Electrical Idle Inference Conditions
rx_elecidleinfersel
[2..0]
3'b100
3'b101
3'b101
3'b110
3'b111
Link Training and Status
State Machine State
Description
L0
Absence of update_FC or alternatively skip ordered set in 128 s
window
Recovery.RcvrCfg
Absence of TS1 or TS2 ordered set in 1280 UI interval
Recovery.Speed when
successful speed
negotiation = 1'b1
Absence of TS1 or TS2 ordered set in 1280 UI interval
Recovery.Speed when
successful speed
negotiation = 1'b0
Absence of an exit from electrical idle in 2000 UI interval
Loopback.Active (as slave) Absence of an exit from electrical idle in 128 s window
The electrical idle inference module drives the pipeelecidle signal high in each
receiver channel when an electrical idle condition is inferred. The electrical idle
inference module cannot detect electrical idle exit condition based on the reception of
the electrical idle exit ordered set, as specified in the PCI Express (PIPE) Base
Specification.
1 When enabled, the electrical idle inference block uses electrical idle ordered set
detection from the fast recovery circuitry to drive the pipeelecidle signal.
Compliance Pattern Transmission
In PIPE mode, the Cyclone IV GX transceiver supports compliance pattern
transmission which requires the first /K28.5/ code group of the compliance pattern to
be encoded with negative current disparity. This requirement is supported using a
tx_forcedispcompliance port that when driven with logic high, the transmitter data
on the tx_datain port is transmitted with negative current running disparity.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2