EP4CE30F29C7N Datasheet, PDF (214/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–50
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board
buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system with JTAG BST circuitry. Figure 8–25 and Figure 8–26
show multi-device JTAG configuration.
For devices using 2.5-, 3.0-, and 3.3-V V_CCIO supply, you must refer to Figure 8–25. All
I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not
have the internal PCI clamping diodes to prevent voltage overshoot when using 2.5-,
3.0-, and 3.3- V V_CCIO supply. You must power up the V_CC of the download cable with
a 2.5-V V_CCA supply. For device using V_CCIO of 1.2, 1.5 V, and 1.8 V, refer to
Figure 8–26. You can power up the V_CC of the download cable with the supply from
V_CCIO.
Figure 8–25. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V V_CCIO Powering the
JTAG Pins)
Download Cable
10-Pin Male Header
V_CCA
V_CCIO(1)
VCCIO(1)
Pin 1
V_{CCA (5) VCCA}
(6)
VIO
(3)
(6)
(2)
(2)
(2)
(2)
(2)
10 kΩ Cyclone IV Device
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[ ]
nCEO
nCE (4)
CONF_DONE
10 kΩ
V_{CCIO (1)}
V_{CCIO (1)}
V_CCIO (1)
V_CCIO (1)
10 kΩ _{Cyclone IV Device}
10 kΩ
10 kΩ _{Cyclone IV Device}
10 kΩ
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG CONF_DONE
(2)
MSEL[ ]
(2)
nCEO
nCE (4)
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG CONF_DONE
(2) MSEL[ ]
(2)
nCEO
nCE (4)
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
1 kΩ
Notes to Figure 8–25:
(1) Connect these pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the nCONFIG
pin to logic-high and the MSEL pins to GND. In addition, pull DCLK and DATA[0] to either high or low, whichever is convenient on your board.
(3) Pin 6 of the header is a V_IO reference voltage for the MasterBlaster output driver. V_IO must match the V_CCA of the device. For this value, refer to the
MasterBlaster Serial/USB Communications Cable User Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and
ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
(4) You must connect the nCE pin to GND or driven low for successful JTAG configuration.
(5) Power up the V_CC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5-V supply from V_CCA. Third-party programmers must switch
to 2.5 V. Pin 4 of the header is a V_CC power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V
circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User
Guide.
(6) Resistor value can vary from 1 kΩ to 10 kΩ.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation