EP4CE30F29C7N Datasheet, PDF (372/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–92
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–29. Multipurpose PLL, General Purpose PLL and Miscellaneous Ports in ALTGX Megafunction for
Cyclone IV GX (Part 2 of 2)
Block
Port Name
gxb_powerdown
Reset & Power
Down
tx_digitalreset
rx_analogreset
rx_digitalreset
reconfig_clk
Reconfiguration
reconfig_togxb
reconfig_fromgxb
cal_blk_clk
Calibration Block
cal_blk_powerdown
rx_bistdone
Test Mode
rx_bisterr
Input/
Output
Clock Domain
Description
Transceiver block power down.
■ When asserted, all digital and analog circuitry in the PCS,
Input Asynchronous signal HSSI, CDR, and PCIe modules are powered down.
■ Asserting the gxb_powerdown signal does not power
down the refclk buffers.
Input
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Transmitter PCS reset.
■ When asserted, the transmitter PCS blocks are reset.
Input
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Receiver PMA reset.
■ When asserted, analog circuitry in the receiver PMA block
is reset.
Input
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Receiver PCS reset.
■ When asserted, the receiver PCS blocks are reset.
Dynamic reconfiguration clock.
Input Clock signal
■ Also used for offset cancellation except in PIPE mode.
■ For the supported frequency range for this clock, refer to
the Cyclone IV Device Data Sheet chapter.
Input Asynchronous signal From the dynamic reconfiguration controller.
Output Asynchronous signal To the dynamic reconfiguration controller.
Input Clock signal
Clock for the transceiver calibration block.
Input Asynchronous signal Calibration block power down control.
BIST or PRBS test completion indicator.
Output Asynchronous signal
■ A high level during BIST test mode indicates the verifier
either receives complete pattern cycle or detects an error
and stays asserted until being reset using the
rx_digitalreset port.
■ A high level during PRBS test mode indicates the verifier
receives complete pattern cycle and stays asserted until
being reset using the rx_digitalreset port.
BIST or PRBS verifier error indicator
■ In BIST test mode, the signal stays asserted upon detecting
an error until being reset using the rx_digitalreset
Output Asynchronous signal port.
■ In PRBS test mode, the signal asserts for a minimum of 3
rx_clkout clock cycles upon detecting an error and
deasserts if the following PRBS sequence contains no error.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation