EP4CE30F29C7N Datasheet, PDF (72/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

5–10
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
If you do not use dedicated clock pins to feed the GCLKs, you can use them as
general-purpose input pins to feed the logic array. However, when using them as
general-purpose input pins, they do not have support for an I/O register and must
use LE-based registers in place of an I/O register.
f For more information about how to connect the clock and PLL pins, refer to the
Cyclone IV Device Family Pin Connection Guidelines.
Clock Control Block
The clock control block drives the GCLKs. Clock control blocks are located on each
side of the device, close to the dedicated clock input pins. GCLKs are optimized for
minimum clock skew and delay.
Table 5–4 lists the sources that can feed the clock control block, which in turn feeds the
GCLKs.
Table 5–4. Clock Control Block Inputs
Input
Dedicated clock inputs
Dual-purpose clock
(DPCLK and CDPCLK)
I/O input
PLL outputs
Internal logic
Description
Dedicated clock input pins can drive clocks or global signals, such as
synchronous and asynchronous clears, presets, or clock enables onto
given GCLKs.
DPCLK and CDPCLK I/O pins are bidirectional dual function pins that
are used for high fan-out control signals, such as protocol signals,
TRDY and IRDY signals for PCI, via the GCLK. Clock control blocks
that have inputs driven by dual-purpose clock I/O pins are not able to
drive PLL inputs.
PLL counter outputs can drive the GCLK.
You can drive the GCLK through logic array routing to enable internal
logic elements (LEs) to drive a high fan-out, low-skew signal path.
Clock control blocks that have inputs driven by internal logic are not
able to drive PLL inputs.
In Cyclone IV devices, dedicated clock input pins, PLL counter outputs, dual-purpose
clock I/O inputs, and internal logic can all feed the clock control block for each GCLK.
The output from the clock control block in turn feeds the corresponding GCLK. The
GCLK can drive the PLL input if the clock control block inputs are outputs of another
PLL or dedicated clock input pins. There are five or six clock control blocks on each
side of the device periphery—depending on device density; providing up to 30 clock
control blocks in each Cyclone IV GX device. The maximum number of clock control
blocks per Cyclone IV E device is 20. For the clock control block locations, refer to
Figure 5–2 on page 5–12, Figure 5–3 on page 5–13, and Figure 5–4 on page 5–14.
1 The clock control blocks on the left side of the Cyclone IV GX device do not support
any clock inputs.
The control block has two functions:
■ Dynamic GCLK clock source selection (not applicable for DPCLK, CDPCLK, and
internal logic input)
■ GCLK network power down (dynamic enable and disable)
Cyclone IV Device Handbook,
Volume 1
October 2012 Altera Corporation