EP4CE30F29C7N Datasheet, PDF (414/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

3–16
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–5 shows the read transaction waveform for Method 1.
Figure 3–5. Read Transaction Waveform—Use ‘logical_channel_address port’ Option
reconfig_clk
read
rx_tx_duplex_sel [1:0] (1)
2'b00
2'b10
logical_channel_address [1:0] (2)
2'b00
2'b01
busy
data_valid
tx_vodctrl_out [2:0]
3'b111
3'bXXX
3'b001
Notes to Figure 3–5:
(1) In this waveform example, you want to read from only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
logical_channel_address port is 2 bits wide.
1 Simultaneous write and read transactions are not allowed.
Method 2: Writing the Same Control Signals to Control All the Transceiver
Channels
This method does not require the logical_channel_address port. The PMA controls
of all the transceiver channels connected to the ALTGX_RECONFIG instance are
reconfigured.
The Use the same control signal for all the channels option is available on the
Analog controls tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager. If you
enable this option, the width of the PMA control ports are fixed as follows:
PMA Control Ports Used in a Write Transaction
■ tx_vodctrl is fixed to 3 bits
■ tx_preemp is fixed to 5 bits
■ rx_eqdcgain is fixed to 2 bits
■ rx_eqctrl is fixed to 4 bits
Cyclone IV Device Handbook,
Volume 2
November 2011 Altera Corporation