EP4CE30F29C7N Datasheet, PDF (376/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

2–2
Chapter 2: Cyclone IV Reset Control and Power Down
User Reset and Power-Down Signals
User Reset and Power-Down Signals
Each transceiver channel in the Cyclone IV GX device has individual reset signals to
reset its physical coding sublayer (PCS) and physical medium attachment (PMA). The
transceiver block also has a power-down signal that affects the multipurpose
phase-locked loops (PLLs), general purpose PLLs, and all the channels in the
transceiver block.
1 All reset and power-down signals are asynchronous.
Table 2–1 lists the reset signals available for each transceiver channel.
Table 2–1. Transceiver Channel Reset Signals
Signal
ALTGX MegaWizard Plug-In
Manager Configurations
Description
tx_digitalreset ⁽¹⁾
■ Transmitter Only
■ Receiver and Transmitter
Provides asynchronous reset to all digital logic in
the transmitter PCS, including the XAUI transmit
state machine.
The minimum pulse width for this signal is two
parallel clock cycles.
rx_digitalreset ⁽¹⁾
■ Receiver Only
■ Receiver and Transmitter
Resets all digital logic in the receiver PCS,
including:
■ XAUI receiver state machines
■ GIGE receiver state machines
■ XAUI channel alignment state machine
■ BIST-PRBS verifier
■ BIST-incremental verifier
The minimum pulse width for this signal is two
parallel clock cycles.
rx_analogreset
■ Receiver Only
■ Receiver and Transmitter
Resets the receiver CDR present in the receiver
channel.
The minimum pulse width is two parallel clock
cycles.
Note to Table 2–1:
(1) Assert this signal until the clocks coming out of the multipurpose PLL and receiver CDR are stabilized. Stable parallel clocks are essential for
proper operation of transmitter and receiver phase-compensation FIFOs in the PCS.
Cyclone IV Device Handbook,
Volume 2
May 2013 Altera Corporation