EP4CE30F29C7N Datasheet, PDF (73/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
Figure 5–1 shows the clock control block.
Figure 5–1. Clock Control Block
Static Clock Select (3)
Internal Logic
DPCLK
5–11
Clock Control Block
Enable/
Disable
Global
Clock
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n] (6)
inclk1
inclk0
C0
C1
f_{IN PLL C2}
C3
CLKSWITCH (1)
C4
inclk1
inclk0
C0
C1
f_{IN PLL C2}
C3
Not applicable to
Cyclone IV E devices ^{CLKSWITCH (1)}
C4
Static Clock
Select (3)
CLKSELECT[1..0] (2) ^{Internal Logic (5)}
(4)
Notes to Figure 5–1:
(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
output of the multiplexer is the input clock (f_IN) for the PLL.
(2) The clkselect[1..0] signals are fed by internal logic and are used to dynamically select the clock source for the GCLK when the device is in
user mode.
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) Two out of four PLL clock outputs are selected from adjacent PLLs to drive into the clock control block.
(5) You can use internal logic to enable or disable the GCLK in user mode.
(6) CLK[n] is not available on the left side of Cyclone IV E devices.
Each PLL generates five clock outputs through the c[4..0] counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in Figure 5–1.
f For more information about how to use the clock control block in the Quartus II
software, refer to the ALTCLKCTRL Megafunction User Guide.
October 2012 Altera Corporation
Cyclone IV Device Handbook,
Volume 1