EP4CE30F29C7N Datasheet, PDF (63/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

October 2012
CYIV-51005-2.4
CYIV-51005-2.4
5. Clock Networks and PLLs in
Cyclone IV Devices
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
with advanced features in the Cyclone^® IV device family. It includes details about the
ability to reconfigure the PLL counter clock frequency and phase shift in real time,
allowing you to sweep PLL output frequencies and dynamically adjust the output
clock phase shift.
1 The Quartus^® II software enables the PLLs and their features without external
devices.
This chapter contains the following sections:
■ “Clock Networks” on page 5–1
■ “PLLs in Cyclone IV Devices” on page 5–18
■ “Cyclone IV PLL Hardware Overview” on page 5–20
■ “Clock Feedback Modes” on page 5–23
■ “Hardware Features” on page 5–26
■ “Programmable Bandwidth” on page 5–32
■ “Phase Shift Implementation” on page 5–32
■ “PLL Cascading” on page 5–33
■ “PLL Reconfiguration” on page 5–34
■ “Spread-Spectrum Clocking” on page 5–41
■ “PLL Specifications” on page 5–41
Clock Networks
The Cyclone IV GX device provides up to 12 dedicated clock pins (CLK[15..4]) that
can drive the global clocks (GCLKs). Cyclone IV GX devices support four dedicated
clock pins on each side of the device except the left side. These clock pins can drive up
to 30 GCLKs.
The Cyclone IV E device provides up to 15 dedicated clock pins (CLK[15..1]) that can
drive up to 20 GCLKs. Cyclone IV E devices support three dedicated clock pins on the
left side and four dedicated clock pins on the top, right, and bottom sides of the device
except EP4CE6 and EP4CE10 devices. EP4CE6 and EP4CE10 devices only support
three dedicated clock pins on the left side and four dedicated clock pins on the right
side of the device.
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Cyclone IV Device Handbook,
Volume 1
October 2012
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