EP4CE30F29C7N Datasheet, PDF (253/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 9: SEU Mitigation in Cyclone IV Devices
9–7
Software Support
1 The divisor value divides the frequency of the configuration oscillator
output clock. This output clock is used as the clock source for the error
detection process.
8. Click OK.
Figure 9–2. Enabling the Error Detection CRC Feature in the Quartus II Software
Accessing Error Detection Block Through User Logic
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register, which is read out by user logic from the core. The cycloneiv_crcblock
primitive is a WYSIWYG component used to establish the interface from the user
logic to the error detection circuit. The cycloneiv_crcblock primitive atom contains
the input and output ports that must be included in the atom. To access the logic
array, the cycloneiv_crcblock WYSIWYG atom must be inserted into your design.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1