EP4CE30F29C7N Datasheet, PDF (149/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 7: External Memory Interfaces in Cyclone IV Devices
7–3
Cyclone IV Devices Memory Interfaces Pin Support
In Cyclone IV devices, DQS is used only during write mode in DDR2 and
DDR SDRAM interfaces. Cyclone IV devices ignore DQS as the read-data strobe
because the PHY internally generates the read capture clock for read mode. However,
you must connect the DQS pin to the DQS signal in DDR2 and DDR SDRAM interfaces,
or to the CQ signal in QDR II SRAM interfaces.
1 Cyclone IV devices do not support differential strobe pins, which is an optional
feature in the DDR2 SDRAM device.
f When you use the Altera Memory Controller MegaCore^® function, the PHY is
instantiated for you. For more information about the memory interface data path,
refer to the External Memory Interface Handbook.
1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the
implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone IV devices through the
ALTMEMPHY megafunction because you are not required to route the DQS signals on
the global clock buses (because DQS is ignored for read capture). Resynchronization
issues do not arise because no transfer occurs from the memory domain clock (DQS) to
the system domain for capturing data DQ.
All I/O banks in Cyclone IV devices can support DQ and DQS signals with DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36 except Cyclone IV GX devices that do not
support left I/O bank interface. DDR2 and DDR SDRAM interfaces use ×8 mode DQS
group regardless of the interface width. For a wider interface, you can use multiple ×8
DQ groups to achieve the desired width requirement.
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or four
parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support the
QDR II memory interface. CQ# is the inverted read-clock signal that is connected to
the complementary data strobe (DQS or CQ#) pin. You can use any unused DQ pins as
regular user I/O pins if they are not used as memory interface signals.
f For more information about unsupported DQS and DQ groups of the Cyclone IV
transceivers that run at ≥2.97 Gbps data rate, refer to the Cyclone IV Device Family Pin
Connection Guidelines.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1