EP4CE30F29C7N Datasheet, PDF (367/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
1–87
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 1 of 3)
Block Port Name
rx_syncstatus
rx_patternde
tect
rx_bitslip
RX PCS
rx_rlv
rx_invpolarity
rx_enapattern
align
rx_rmfifodata
inserted
rx_rmfifodata
deleted
Input/
Output
Clock Domain
Output
Synchronous to tx_clkout (non-
bonded modes with rate match
FIFO), rx_clkout (non-bonded
modes without rate match FIFO),
coreclkout (bonded modes), or
rx_coreclk (when using the
optional rx_coreclk input)
Output
Synchronous to tx_clkout (non-
bonded modes with rate match
FIFO), rx_clkout (non-bonded
modes without rate match FIFO),
coreclkout (bonded modes), or
rx_coreclk (when using the
optional rx_coreclk input)
Asynchronous signal. Minimum
Input pulse width is two
parallel clock cycles.
Output
Asynchronous signal. Driven for a
minimum of two recovered clock
cycles in configurations without
byte serializer and a minimum of
three recovered clock cycles in
configurations with byte serializer.
Asynchronous signal. Minimum
Input pulse width is two parallel clock
cycles.
Input Asynchronous signal.
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Description
Word alignment synchronization status indicator. This
signal passes through the RX Phase Compensation FIFO.
■ Not available in bit-slip mode
Indicates when the word alignment logic detects the
alignment pattern in the current word boundary. This
signal passes through the RX Phase Compensation FIFO.
Bit-slip control for the word aligner configured in bit-slip
mode.
■ At every rising edge, word aligner slips one bit into
the received data stream, effectively shifting the word
boundary by one bit.
Run-length violation indicator.
■ A high pulse indicates that the number of consecutive
1s or 0s in the received data stream exceeds the
programmed run length violation threshold.
Generic receiver polarity inversion control.
■ A high level to invert the polarity of every bit of the 8-
or 10-bit data to the word aligner.
Controls the word aligner operation configured in
manual alignment mode.
Rate match FIFO insertion status indicator.
■ A high level indicates the rate match pattern byte is
inserted to compensate for the ppm difference in the
reference clock frequencies between the upstream
transmitter and the local receiver.
Rate match FIFO deletion status indicator.
■ A high level indicates the rate match pattern byte is
deleted to compensate for the ppm difference in the
reference clock frequencies between the upstream
transmitter and the local receiver.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2