EP4CE30F29C7N Datasheet, PDF (251/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 9: SEU Mitigation in Cyclone IV Devices
9–5
Error Detection Timing
Table 9–4 defines the registers shown in Figure 9–1.
Table 9–4. Error Detection Registers
Register
32-bit signature
register
32-bit storage register
Function
This register contains the CRC signature. The signature register contains the result of the user
mode calculated CRC value compared against the pre-calculated CRC value. If no errors are
detected, the signature register is all zeros. A non-zero signature register indicates an error in the
configuration CRAM contents.
The CRC_ERROR signal is derived from the contents of this register.
This register is loaded with the 32-bit pre-computed CRC signature at the end of the configuration
stage. The signature is then loaded into the 32-bit CRC circuit (called the Compute and Compare
CRC block, as shown in Figure 9–1) during user mode to calculate the CRC error. This register
forms a 32-bit scan chain during execution of the CHANGE_EDREG JTAG instruction. The
CHANGE_EDREG JTAG instruction can change the content of the storage register. Therefore, the
functionality of the error detection CRC circuitry is checked in-system by executing the instruction
to inject an error during the operation. The operation of the device is not halted when issuing the
CHANGE_EDREG instruction.
Error Detection Timing
When the error detection CRC feature is enabled through the Quartus II software, the
device automatically activates the CRC process upon entering user mode after
configuration and initialization is complete.
The CRC_ERROR pin is driven low until the error detection circuitry detects a corrupted
bit in the previous CRC calculation. After the pin goes high, it remains high during
the next CRC calculation. This pin does not log the previous CRC calculation. If the
new CRC calculation does not contain any corrupted bits, the CRC_ERROR pin is driven
low. The error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
Table 9–5 lists the minimum and maximum error detection frequencies.
Table 9–5. Minimum and Maximum Error Detection Frequencies for Cyclone IV Devices
Error Detection
Frequency
80 MHz/2ⁿ
Maximum Error
Detection Frequency
80 MHz
Minimum Error
Detection Frequency
312.5 kHz
Valid Divisors (2ⁿ)
0, 1, 2, 3, 4, 5, 6, 7, 8
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to “Software Support”). The divisor is a power
of two (2), where n is between 0 and 8. The divisor ranges from one through 256. Refer
to Equation 9–1.
Equation 9–1.
rror detection frequency
=
--⁸---⁰----^M------^H----
2ⁿ
CRC calculation time depends on the device and the error detection clock frequency.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1