EP4CE30F29C7N Datasheet, PDF (205/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
8–41
FPP Configuration Using an External Host
FPP configuration using an external host provides a fast method to configure
Cyclone IV devices. In the FPP configuration scheme, you can use an external host
device to control the transfer of configuration data from a storage device, such as flash
memory, to the target Cyclone IV device. You can store configuration data in an .rbf,
.hex, or .ttf format. When using the external host, a design that controls the
configuration process, such as fetching the data from flash memory and sending it to
the device, must be stored in the external host device. Figure 8–19 shows the
configuration interface connections between the Cyclone IV devices and an external
device for single-device configuration.
Figure 8–19. Single-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
V_CCIO(1) V_CCIO(1)
10 k 10 k
External Host
(MAX II Device or
Microprocessor)
GND
Cyclone IV Device
MSEL[3..0]
CONF_DONE
nSTATUS
nCE
nCEO
(3)
N.C. (2)
DATA[7..0] ⁽⁴⁾
nCONFIG
DCLK ⁽⁴⁾
Notes to Figure 8–19:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V_CC must be high
enough to meet the V_IH specification of the I/O on the device and the external host.
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
refer to Table 8–4 on page 8–8 and Table 8–5 on page 8–9. Connect the MSEL pins directly to V_CCA or GND.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum overshoot
outlined in Equation 8–1 on page 8–5.
After nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the external host device
places the configuration data one byte at a time on the DATA[7..0]pins.
Cyclone IV devices receive configuration data on the DATA[7..0] pins and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Data is continuously clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin goes high one byte early in FPP configuration mode. The last byte is
required for serial configuration (AS and PS) modes.
1 Two DCLK falling edges are required after CONF_DONE goes high to begin initialization
of the device.
Supplying a clock on CLKUSR does not affect the configuration process. After the
CONF_DONE pin goes high, CLKUSR is enabled after the time specified as t_CD2CU. After
this time period elapses, Cyclone IV devices require 3,192 clock cycles to initialize
properly and enter user mode. For more information about the supported CLKUSR f_MAX
value for Cyclone IV devices, refer to Table 8–13 on page 8–44.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1