EP4CE30F29C7N Datasheet, PDF (358/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–78
Chapter 1: Cyclone IV Transceivers Architecture
Loopback
Figure 1–69 shows the transceiver configuration in SDI mode.
Figure 1–69. Transceiver Configuration in SDI Mode
Functional Mode
SDI
Channel Bonding
×1 (HD or 3G)
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Disabled
Bit Slip
(7-bit, 10-Bit)
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Disabled
Disabled
Enabled
Disabled
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
HD - 1.4835/1.485
3G - 2.967/2.97
Disabled
20-Bit
HD - 74.175/74.25
3G - 148.35/148.5
HD - 1.4835/1.485
HD - 1.4835/1.485
3G - 2.967/2.97
Disabled
Disabled
10-Bit
20-Bit
HD - 74.175/74.25
HD - 74.175/74.25
3G - 148.35/148.5
HD - 1.4835/1.485
Disabled
10-Bit
HD - 74.175/74.25
1 Altera recommends driving rx_bitslip port low in configuration where low-latency
PCS is not enabled. In SDI systems, the word alignment and framing occurs after de-
scrambling, which is implemented in the user logic. The word alignment therefore is
not useful, and keeping rx_bitslip port low avoids the word aligner from inserting
bits in the received data stream.
Loopback
Cyclone IV GX devices provide three loopback options that allow you to verify the
operation of different functional blocks in the transceiver channel. The following
loopback modes are available:
■ reverse parallel loopback (available only for PIPE mode)
■ serial loopback (available for all modes except PIPE mode)
■ reverse serial loopback (available for all modes except XAUI mode)
1 In each loopback mode, all transmitter buffer and receiver buffer settings are available
if the buffers are active, unless stated otherwise.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation