EP4CE30F29C7N Datasheet, PDF (49/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
3–13
Figure 3–12 shows the Cyclone IV devices M9K memory block in shift register mode.
Figure 3–12. Cyclone IV Devices Shift Register Mode Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
m-Bit Shift Register
W
m-Bit Shift Register
W
n Number of Taps
W
W
ROM Mode
Cyclone IV devices M9K memory blocks support ROM mode. A .mif initializes the
ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
FIFO Buffer Mode
Cyclone IV devices M9K memory blocks support single-clock or dual-clock FIFO
buffers. Dual clock FIFO buffers are useful when transferring data from one clock
domain to another clock domain. Cyclone IV devices M9K memory blocks do not
support simultaneous read and write from an empty FIFO buffer.
f For more information about FIFO buffers, refer to the Single- and Dual-Clock FIFO
Megafunction User Guide.
November 2011 Altera Corporation
Cyclone IV Device Handbook,
Volume 1