EP4CE30F29C7N Datasheet, PDF (188/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–24
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–7 shows the interface for the Micron P30 flash memory and P33 flash
memory to the Cyclone IV E device pins.
Figure 8–7. Single-Device AP Configuration Using Micron P30 and P33 Flash Memory
VCCIO (1) VCCIO (1) VCCIO (1)
10k
10k
10k
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
Micron P30/P33 Flash
nCEO
nCE
GND
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (4)
DATA[15..0]
PADD[23..0]
MSEL[3..0]
Cyclone IV E Device
N.C. (2)
(3)
Notes to Figure 8–7:
(1) Connect the pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 8–5 on page 8–9.
Connect the MSEL pins directly to V_CCA or GND.
(4) AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic, you
can optionally use normal I/O to monitor the WAIT signal from the Micron P30 or P33 flash.
1 To tri-state the configuration bus for AP configuration schemes, you must tie nCE high
and nCONFIG low.
1 In a single-device AP configuration, the maximum board loading and board trace
length between supported parallel flash and Cyclone IV E devices must follow the
recommendations listed in Table 8–11 on page 8–28.
1 If you use the AP configuration scheme for Cyclone IV E devices, the V_CCIO of I/O
banks 1, 6, 7, and 8 must be 3.3, 3.0, 2.5, or 1.8 V. Altera does not recommend using the
level shifter between the Micron P30 or P33 flash and the Cyclone IV E device in the
AP configuration scheme.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation