EP4CE30F29C7N Datasheet, PDF (329/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
1–49
Figure 1–45 and Figure 1–46 show the supported transceiver configurations in Basic
mode with the 8-bit and 10-bit PMA-PCS interface width respectively.
Figure 1–45. Supported Transceiver Configurations in Basic Mode with the 8-bit PMA-PCS
Interface Width
Functional Mode
Basic (8-Bit PMA-PCS Interface Width)
Channel Bonding
×1, ×2, ×4
Low-Latency PCS
Disabled
Enabled
Word Aligner (Pattern Length)
Manual Alignment
(16-Bit)
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Disabled
Byte SERDES
Disabled
Enabled
Bit Slip
(16-Bit)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled Enabled Disabled Enabled
Data Rate (Gbps)
0.6-
0.6-
0.6-
0.6-
0.6-
0.6-
1.0
2.0
1.0
1.0
1.0
1.0
0.6-
0.6-
0.6-
0.6-
0.6-
0.6-
1.25
2.5
1.25
2.5
1.25
1.25
Byte Ordering
Disabled Disabled Enabled Disabled Disabled Disabled Disabled
FPGA Fabric-to-Transceiver
Interface Width
8-Bit
16-Bit 16-Bit
8-Bit
16-Bit
8-Bit 16-Bit
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
75-
125
75-
156.25
37.5-
125
37.5-
156.25
37.5-
125
37.5-
156.25
75-
125
75-
156.25
37.5-
125
37.5-
156.25
75-
125
75-
156.25
37.5-
125
37.5-
156.25
Applicable for devices in
F324 and smaller packages
Applicable for devices in
F484 and larger packages
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2