EP4CE30F29C7N Datasheet, PDF (387/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
2–13
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and a receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in automatic lock mode, use the reset sequence shown in Figure 2–8.
Figure 2–8. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
Reset Signals
1
pll_areset
tx_digitalreset
1 μs
2
rx_analogreset
rx_digitalreset
Output Status Signals
busy (2)
pll_locked
4
6
Two parallel clock cycles
5
3
8
7
rx_freqlocked
t_{LTD_Auto} (1)
Notes to Figure 2–8:
(1) For t_{LTD_Auto} duration, refer to the Cyclone IV Device Datasheet chapter.
(2) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the busy
signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
As shown in Figure 2–8, perform the following reset procedure for the receiver in
CDR automatic lock mode:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
between markers 1 and 2).
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
asserted during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the transmitter input reference clock.
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
high (marker 3), deassert tx_digitalreset. For receiver operation, after
deassertion of busy signal, wait for two parallel clock cycles to deassert the
rx_analogreset signal.
4. Wait for the rx_freqlocked signal to go high (marker 7).
5. After the rx_freqlocked signal goes high, wait for at least t_{LTD_Auto}, then deassert
the rx_digitalreset signal (marker 8). At this point, the transmitter and receiver
are ready for data traffic.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2