EP4CE30F29C7N Datasheet, PDF (285/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
1–5
Transmitter Channel Datapath
Transmitter Channel Datapath
The following sections describe the Cyclone IV GX transmitter channel datapath
architecture as shown in Figure 1–3:
■ TX Phase Compensation FIFO
■ Byte Serializer
■ 8B/10B Encoder
■ Serializer
■ Transmitter Output Buffer
TX Phase Compensation FIFO
The TX phase compensation FIFO compensates for the phase difference between the
low-speed parallel clock and the FPGA fabric interface clock, when interfacing the
transmitter channel to the FPGA fabric (directly or through the PIPE and
PCIe hard IP). The FIFO is four words deep, with latency between two to three
parallel clock cycles. Figure 1–4 shows the TX phase compensation FIFO block
diagram.
Figure 1–4. TX Phase Compensation FIFO Block Diagram
tx_datain[x..0] (1)
TX Phase
Compensation
FIFO
wr_clk
rd_clk
tx_phase_comp_fifo_error
Data output to
the byte serializer
or the 8B/10B encoder
Note to Figure 1–4:
(1) The x refers to the supported 8-, 10-, 16-, or 20-bits transceiver channel width.
1 The FIFO can operate in registered mode, contributing to only one parallel clock cycle
of latency in Deterministic Latency functional mode. For more information, refer to
“Deterministic Latency Mode” on page 1–73.
f For more information about FIFO clocking, refer to “FPGA Fabric-Transceiver
Interface Clocking” on page 1–43.
Byte Serializer
The byte serializer divides the input datapath width by two to allow transmitter
channel operation at higher data rates while meeting the maximum FPGA fabric
frequency limit. This module is required in configurations that exceed the maximum
FPGA fabric-transceiver interface clock frequency limit and optional in configurations
that do not.
f For the FPGA fabric-transceiver interface frequency specifications, refer to the Cyclone
IV Device Data Sheet.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2