EP4CE30F29C7N Datasheet, PDF (212/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–48
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–24. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V V_CCIO
Powering the JTAG Pins)
V_CCIO (1)
V_CCIO (1) _{10 kΩ}
10 kΩ
GND
N.C. (5)
(2)
(2)
(2)
(2)
V_CCIO
(7)
V_CCIO
Cyclone IV Device
(7)
nCE (4)
TCK
TDO
nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL[ ]
DATA[0]
DCLK
TMS
TDI
Download Cable 10-Pin Male
Header (Top View)
Pin 1
V_CCIO (6)
GND
V_IO (3)
1 kΩ
GND
GND
Notes to Figure 8–24:
(1) Connect these pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use JTAG
configuration, connect the nCONFIG pin to logic-high and the MSEL pins to GND. In addition, pull DCLK and DATA[0]
to either high or low, whichever is convenient on your board.
(3) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming;
otherwise it is a no connect.
(4) The nCE must be connected to GND or driven low for successful JTAG configuration.
(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(6) Power up the V_CC of the EthernetBlaster, ByteBlaster II or USB-Blaster cable with supply from V_CCIO. The
Ethernet-Blaster, ByteBlaster II, and USB-Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the ByteBlaster II Download Cable User Guide, the USB-Blaster Download Cable User
Guide, and the EthernetBlaster Communications Cable User Guide.
(7) Resistor value can vary from 1 kΩ to 10 kΩ.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration after completion. At
the end of configuration, the software checks the state of CONF_DONE through the JTAG
port. When Quartus II generates a .jam for a multi-device chain, it contains
instructions so that all the devices in the chain are initialized at the same time. If
CONF_DONE is not high, the Quartus II software indicates that configuration has failed.
If CONF_DONE is high, the software indicates that configuration was successful. After
the configuration bitstream is serially sent using the JTAG TDI port, the TCK port
clocks an additional clock cycles to perform device initialization.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation