EP4CE30F29C7N Datasheet, PDF (296/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–16
Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Actual lock time depends on the transition density of the incoming data and the ppm
difference between the receiver input reference clock and the upstream transmitter
reference clock.
Transition from the LTD state to the LTR state occurs when either of the following
conditions is met:
■ Signal detection circuitry indicates the absence of valid signal levels at the receiver
input buffer. This condition is valid for PCI Express (PIPE) mode only. CDR
transitions are not dependent on signal detection circuitry in other modes.
■ The recovered clock is not within the configured ppm frequency threshold setting
with respect to CDR clocks from multipurpose PLLs.
In automatic lock mode, the switch from LTR to LTD states is indicated by the
assertion of the rx_freqlocked signal and the switch from LTD to LTR states indicated
by the de-assertion of the rx_freqlocked signal.
Manual Lock Mode
State transitions are controlled manually by using rx_locktorefclk and
rx_locktodata ports. The LTR/LTD controller sets the CDR state depending on the
logic level on the rx_locktorefclk and rx_locktodata ports. This mode provides the
flexibility to control the CDR for a reduced lock time compared to the automatic lock
mode. In automatic lock mode, the LTR/LTD controller relies on the ppm detector
and the phase relationship detector to set the CDR in LTR or LTD mode. The ppm
detector and phase relationship detector reaction times can be too long for some
applications that require faster CDR lock time.
In manual lock mode, the rx_freqlocked signal is asserted when the CDR is in LTD
state and de-asserted when CDR is in LTR state. For descriptions of rx_locktorefclk
and rx_locktodata port controls, refer to Table 1–27 on page 1–87.
1 If you do not enable the optional rx_locktorefclk and rx_locktodata ports, the
Quartus II software automatically configures the LTR/LTD controller in automatic
lock mode.
f The recommended transceiver reset sequence varies depending on the CDR lock
mode. For more information about the reset sequence recommendations, refer to the
Reset Control and Power Down for Cyclone IV GX Devices chapter.
Deserializer
The deserializer converts received serial data from the receiver input buffer to parallel
8- or 10-bit data. Serial data is assumed to be received from the LSB to the MSB. The
deserializer operates with the high-speed recovered clock from the CDR with the
frequency at half of the serial data rate.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation