EP4CE30F29C7N Datasheet, PDF (304/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–24
Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Byte Deserializer
The byte deserializer halves the FPGA fabric-transceiver interface frequency while
doubles the parallel data width to the FPGA fabric.
For example, when operating an EP4CGX150 receiver channel at 3.125 Gbps with
deserialization factor of 10, the receiver PCS datapath runs at 312.5 MHz. The byte
deserializer converts the 10-bit data at 312.5 MHz into 20-bit data at 156.25 MHz
before forwarding the data to the FPGA fabric.
Byte Ordering
In the 16- or 20-bit FPGA fabric-transceiver interface, the byte deserializer receives
one data byte (8 or 10 bits) and deserializes it into two data bytes (16 or 20 bits).
Depending on when the receiver PCS logic comes out of reset, the byte ordering at the
output of the byte deserializer may not match the original byte ordering of the
transmitted data. The byte misalignment resulting from byte deserialization is
unpredictable because it depends on which byte is being received by the byte
deserializer when it comes out of reset.
Figure 1–23 shows a scenario where the most significant byte and the least significant
byte of the two-byte transmitter data appears straddled across two word boundaries
after the data is deserialized at the receiver.
Figure 1–23. Example of Byte Deserializer at the Receiver
Transmitter
Receiver
tx_datain[15..8] D2
D2
D2
tx_datain[7..0] D1
D1
D1
Byte ^{xx D1 D2 D3 D4 D5 D6 xx}
Byte
Serializer
Deserializer
D1
D3
D5
xx rx_dataout[15..8]
xx
D2
D4
D6 rx_dataout[7..0]
The byte ordering block restores the proper byte ordering by performing the
following actions:
■ Look for the user-programmed byte ordering pattern in the byte-deserialized data
■ Inserts a user-programmed pad byte if the user-programmed byte ordering
pattern is found in the most significant byte position
You must select a byte ordering pattern that you know appears at the least significant
byte position of the parallel transmitter data.
The byte ordering block is supported in the following receiver configurations:
■ 16-bit FPGA fabric-transceiver interface, 8B/10B disabled, and the word aligner in
manual alignment mode. Program a custom 8-bit byte ordering pattern and 8-bit
pad byte.
■ 16-bit FPGA fabric-transceiver interface, 8B/10B enabled, and the word aligner in
automatic synchronization state machine mode. Program a custom 9-bit byte
ordering pattern and 9-bit pad byte. The MSB of the 9-bit byte ordering pattern
and pad byte represents the control identifier of the 8B/10B decoded data.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation