EP4CE30F29C7N Datasheet, PDF (427/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
3–29
Option 1: Share a Single Transmitter Core Clock Between Transmitters
■ Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the write clock to the Transmitter Phase
Compensation FIFOs of the remaining channels in the transceiver block.
■ This option is typically enabled when all the channels of a transceiver block have
the same functional mode and data rate and are reconfigured to the identical
functional mode and data rate.
Figure 3–11 shows the sharing of channel 0’s tx_clkout between all four regular
channels of a transceiver block.
Figure 3–11. Option 1 for Transmitter Core Clocking (Channel Reconfiguration Mode)
FPGA Fabric
Transceiver Block
TX0
RX0
TX1
tx_clkout[0]
RX1
TX2
RX2
TX3
RX3
MPLL
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
November 2011 Altera Corporation
Cyclone IV Device Handbook,
Volume 2