EP4CE30F29C7N Datasheet, PDF (143/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 6: I/O Features in Cyclone IV Devices
Design Guidelines
6–37
Table 6–11. High-Speed I/O Timing Definitions (Part 2 of 2)
Parameter
Symbol
Description
Input jitter tolerance (peak-to-peak)
—
Allowed input jitter on the input clock to the PLL that is tolerable
while maintaining PLL lock.
Output jitter (peak-to-peak)
— Peak-to-peak output jitter from the PLL.
Note to Table 6–11:
(1) The TCCS specification applies to the entire bank of differential I/O as long as the SERDES logic is placed in the logic array block (LAB) adjacent
to the output pins.
Figure 6–21. High-Speed I/O Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal Clock
Receiver
Input Data
TCCS RSKM
Sampling Window (SW)
RSKM TCCS
Figure 6–22 shows the Cyclone IV devices high-speed I/O timing budget.
Figure 6–22. Cyclone IV Devices High-Speed I/O Timing Budget ⁽¹⁾
Internal Clock Period
0.5 × TCCS RSKM
SW
Note to Figure 6–22:
(1) The equation for the high-speed I/O timing budget is:
eriod = 0.5 × TCCS + RSKM + SW + RSKM + 0.5 × TCCS
RSKM
0.5 × TCCS
f For more information, refer to the Cyclone IV Device Datasheet chapter.
Design Guidelines
This section provides guidelines for designing with Cyclone IV devices.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the V_CCIO supply, you must observe some
restrictions on the placement of single-ended I/O pins in relation to differential pads.
1 For guidelines on placing single-ended pads with respect to differential pads in
Cyclone IV devices, refer to “Pad Placement and DC Guidelines” on page 6–23.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1