EP4CE30F29C7N Datasheet, PDF (388/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

2–14
Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in manual lock mode, use the reset sequence shown in Figure 2–9.
Figure 2–9. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
Reset Signals
1 μs
1
pll_areset
tx_digitalreset
2
4
6
rx_analogreset
8
rx_digitalreset
CDR Control Signals
rx_locktorefclk
rx_locktodata
Output Status Signals
busy (3)
pll_locked
t_{LTD_Manual} (2)
7
t_{LTR_LTD_Manual} (1)
7
Two parallel clock cycles
5
3
rx_pll_locked
Notes to Figure 2–9:
(1) For t_{LTR_LTD_Manual} duration, refer to the Cyclone IV Device Datasheet chapter.
(2) For t_{LTD_Manual} duration, refer to the Cyclone IV Device Datasheet chapter.
(3) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the busy
signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
As shown in Figure 2–9, perform the following reset procedure for the receiver in
manual lock mode:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
between markers 1 and 2).
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted during
this time period. After you deassert the pll_areset signal, the multipurpose PLL
starts locking to the transmitter input reference clock.
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
high (marker 3), deassert tx_digitalreset (marker 4). For receiver operation,
after deassertion of busy signal (marker 5), wait for two parallel clock cycles to
deassert the rx_analogreset signal (marker 6). After rx_analogreset deassert,
rx_pll_locked will assert.
Cyclone IV Device Handbook,
Volume 2
May 2013 Altera Corporation