EP4CE30F29C7N Datasheet, PDF (349/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
1–69
Figure 1–63 shows the transceiver channel datapath and clocking when configured in
XAUI mode.
Figure 1–63. Transceiver Channel Datapath and Clocking when Configured in XAUI Mode
FPGA
Fabric
Tx Phase
Comp
FIFO
wr_clk rd_clk
Transmitter Channel PCS 3
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 3
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
/2
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
(1)
(2)
Transmitter Channel PCS 2
Transmitter Channel PMA 3
Serializer
high-speed
clock
Receiver Channel PMA 3
Deserial-
izer
CDR
(3)
CDR clock
Transmitter Channel PMA 2
coreclkout
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 2
Serializer
high-speed
clock
Receiver Channel PMA 2
Rx
Phase
Comp
FIFO
/2
Byte
Order-
ing
Byte
De-
serializer
/2
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
(1)
(2)
Transmitter Channel PCS 1
Deserial-
izer
CDR
(3)
CDR clock
Transmitter Channel PMA 1
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 1
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
/2
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
(1)
(2)
Transmitter Channel PCS 0
Serializer
high-speed
clock
low-speed clock
Receiver Channel PMA 1
Deserial-
izer
CDR
(3)
CDR clock
Transmitter Channel PMA 0
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 0
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
/2
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
(1)
(2)
Serializer
high-speed
clock
Receiver Channel PMA 0
Deserial-
izer
CDR
(3)
CDR clock
Notes to Figure 1–63:
(1) Channel 1 low-speed recovered clock.
(2) Low-speed recovered clock.
(3) High-speed recovered clock.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2