EP4CE30F29C7N Datasheet, PDF (144/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

6–38
Chapter 6: I/O Features in Cyclone IV Devices
Software Overview
Board Design Considerations
This section explains how to achieve the optimal performance from a Cyclone IV I/O
interface and ensure first-time success in implementing a functional design with
optimal signal quality. You must consider the critical issues of controlled impedance
of traces and connectors, differential routing, and termination techniques to get the
best performance from Cyclone IV devices.
Use the following general guidelines to improve signal quality:
■ Base board designs on controlled differential impedance. Calculate and compare
all parameters, such as trace width, trace thickness, and the distance between two
differential traces.
■ Maintain equal distance between traces in differential I/O standard pairs as much
as possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
■ Longer traces have more inductance and capacitance. These traces must be as
short as possible to limit signal integrity issues.
■ Place termination resistors as close to receiver input pins as possible.
■ Use surface mount components.
■ Avoid 90° corners on board traces.
■ Use high-performance connectors.
■ Design backplane and card traces so that trace impedance matches the impedance
of the connector and termination.
■ Keep an equal number of vias for both signal traces.
■ Create equal trace lengths to avoid skew between signals. Unequal trace lengths
result in misplaced crossing points and decrease system margins as the TCCS
value increases.
■ Limit vias because they cause discontinuities.
■ Keep switching transistor-to-transistor logic (TTL) signals away from differential
signals to avoid possible noise coupling.
■ Do not route TTL clock signals to areas under or above the differential signals.
■ Analyze system-level signals.
f For PCB layout guidelines, refer to AN 224: High-Speed Board Layout Guidelines and
AN 315: Guidelines for Designing High-Speed FPGA PCBs.
Software Overview
Cyclone IV devices high-speed I/O system interfaces are created in core logic by a
Quartus II software megafunction because they do not have a dedicated circuit for the
SERDES. Cyclone IV devices use the I/O registers and LE registers to improve the
timing performance and support the SERDES. The Quartus II software allows you to
design your high-speed interfaces using ALTLVDS megafunction. This megafunction
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation