EP4CE30F29C7N Datasheet, PDF (76/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

5–14
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
Figure 5–4. Clock Networks and Clock Control Block Locations in Cyclone IV E Devices
DPCLK[11.10] DPCLK[9..8]
CDPCLK7
CLK[11..8]
CDPCLK6
CDPCLK0
PLL_3
(4)
(3)
(2)
24
2
(3) 4
4
PLL_2
5
Clock
Control
Block (1)
2
(2)
4
DPCLK0
CLK[3..1]
3
DPCLK1
4
Clock
Control
Block (1)
2
GCLK[19..0]
20
20
20
20
GCLK[19..0]
5
Clock
Control
Block (1)
CDPCLK5
DPCLK7
CLK[7..4]
4
DPCLK6
CDPCLK1
4
5
2
(2)
PLL_1
(3)
4
Clock
Control
Block (1)
2
42
2
5
4
4
(2)
(3)
PLL_4
(4)
CDPCLK4
CDPCLK2
CLK[15..12]
DPCLK[3..2] DPCLK[5..4]
CDPCLK3
Notes to Figure 5–4:
(1) There are five clock control blocks on each side.
(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as
general-purpose I/O (GPIO) pins.
(3) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
(4) PLL_3 and PLL_4 are not available in EP4CE6 and EP4CE10 devices.
The inputs to the clock control blocks on each side of the Cyclone IV GX device must
be chosen from among the following clock sources:
■ Four clock input pins
■ Ten PLL counter outputs (five from each adjacent PLLs)
■ Two, four, or six DPCLK pins from the top, bottom, and right sides of the device
■ Five signals from internal logic
Cyclone IV Device Handbook,
Volume 1
October 2012 Altera Corporation