EP4CE30F29C7N Datasheet, PDF (186/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
During device configuration, Cyclone IV E devices read configuration data using the
parallel interface and configure their SRAM cells. This scheme is referred to as the AP
configuration scheme because the device controls the configuration interface. This
scheme contrasts with the FPP configuration scheme, where an external host controls
the interface.
AP Configuration Supported Flash Memories
The AP configuration controller in Cyclone IV E devices is designed to interface with
two industry-standard flash families—the Micron P30 Parallel NOR flash family and
the Micron P33 Parallel NOR flash family. Unlike serial configuration devices, both of
the flash families supported in AP configuration scheme are designed to interface
with microprocessors. By configuring from an industry standard microprocessor flash
which allows access to the flash after entering user mode, the AP configuration
scheme allows you to combine configuration data and user data (microprocessor boot
code) on the same flash memory.
The Micron P30 flash family and the P33 flash family support a continuous
synchronous burst read mode at 40 MHz DCLK frequency for reading data from the
flash. Additionally, the Micron P30 and P33 flash families have identical pin-out and
adopt similar protocols for data access.
1 Cyclone IV E devices use a 40-MHz oscillator for the AP configuration scheme. The
oscillator is the same oscillator used in the Cyclone IV E AS configuration scheme.
Table 8–10 lists the supported families of the commodity parallel flash for the AP
configuration scheme.
Table 8–10. Supported Commodity Flash for AP Configuration Scheme for Cyclone IV E
Devices ⁽¹⁾
Flash Memory Density
Micron P30 Flash Family ⁽²⁾ Micron P33 Flash Family ⁽³⁾
64 Mbit
v
v
128 Mbit
v
v
256 Mbit
v
v
Notes to Table 8–10:
(1) The AP configuration scheme only supports flash memory speed grades of 40 MHz and above.
(2) 3.3- , 3.0-, 2.5-, and 1.8-V I/O options are supported for the Micron P30 flash family.
(3) 3.3-, 3.0- and 2.5-V I/O options are supported for the Micron P33 flash family.
Configuring Cyclone IV E devices from the Micron P30 and P33 family 512-Mbit flash
memory is possible, but you must properly drive the extra address and FLASH_nCE
pins as required by these flash memories.
f To check for supported speed grades and package options, refer to the respective flash
datasheets.
The AP configuration scheme in Cyclone IV E devices supports flash speed grades of
40 MHz and above. However, AP configuration for all these speed grades must be
capped at 40 MHz. The advantage of faster speed grades is realized when your design
in the Cyclone IV E devices accesses flash memory in user mode.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation