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EP4CE30F29C7N Datasheet, PDF (195/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1 | |||
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
8â31
Programming Parallel Flash Memories
Supported parallel flash memories are external non-volatile configuration devices.
They are industry standard microprocessor flash memories. For more information
about the supported families for the commodity parallel flash, refer to Table 8â10 on
page 8â22.
Cyclone IV E devices in a single- or multiple-device chain support in-system
programming of a parallel flash using the JTAG interface with the flash loader
megafunction. The board intelligent host or download cable uses the four JTAG pins
on Cyclone IV E devices to program the parallel flash in system, even if the host or
download cable cannot access the configuration pins of the parallel flash.
f For more information about using the JTAG pins on Cyclone IV E devices to program
the parallel flash in-system, refer to AN 478: Using FPGA-Based Parallel Flash Loader
(PFL) with the Quartus II Software.
In the AP configuration scheme, the default configuration boot address is 0Ã010000
when represented in 16-bit word addressing in the supported parallel flash memory
(Figure 8â12). In the Quartus II software, the default configuration boot address is
0Ã020000 because it is represented in 8-bit byte addressing. Cyclone IV E devices
configure from word address 0Ã010000, which is equivalent to byte address 0Ã020000.
1 The Quartus II software uses byte addressing for the default configuration boot
address. You must set the start address field to 0Ã020000.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1
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