EP4CE30F29C7N Datasheet, PDF (220/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–56
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
If you configure a master device with an SFL design, the master device enters user
mode even though the slave devices in the multiple device chain are not being
configured. The master device enters user mode with a SFL design even though the
CONF_DONE signal is externally held low by the other slave devices in chain.
Figure 8–29 shows the JTAG configuration of a single Cyclone IV device with a SFL
design.
Figure 8–29. Programming Serial Configuration Devices In-System Using the JTAG Interface
V_CCA
V_CCIO (1)
(9)
V_CCIO (1) 10 kΩ
Serial Configuration
10 kΩ
Device
V_CCIO (1)
10 kΩ
GND
N.C. (5)
25 Ω (7)
(2)
DATA
DCLK
nCS
ASDI
Cyclone IV Device
nCE (4)
TCK
TDO
nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL[ ]
DATA[0]
DCLK
nCSO (8)
ASDO (8)
TMS
TDI
Serial
Flash
Loader
V_CCA
(9)
Download Cable 10-Pin Male
Header (Top View)
Pin 1
V_CCA (6)
GND
V_IO (3)
CLKUSR
(10)
1 kΩ
GND
GND
Notes to Figure 8–29:
(1) Connect the pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL for AS
configuration schemes, refer to Table 8–3 on page 8–8, Table 8–4 on page 8–8, and Table 8–5 on page 8–9. Connect
the MSEL pins directly to V_CCA or GND.
(3) Pin 6 of the header is a V_IO reference voltage for the MasterBlaster output driver. The V_IO must match the V_CCA of the
device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. When using the
ByteBlasterMV download cable, this pin is a no connect. When using USB-Blaster, ByteBlaster II, and EthernetBlaster
cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
(4) You must connect the nCE pin to GND or driven low for successful JTAG configuration.
(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(6) Power up the V_CC of the EthernetBlaster, ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V V_CCA supply.
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a V_CC power supply for the MasterBlaster cable.
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.
(7) Connect the series resistor at the near end of the serial configuration device.
(8) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions
as DATA[1] pin in AP and FPP modes.
(9) Resistor value can vary from 1 kΩ to 10 kΩ.
(10) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for
DCLK.
ISP of the Configuration Device
In the second stage, the SFL design in the master device allows you to write the
configuration data for the device chain into the serial configuration device with the
Cyclone IV device JTAG interface. The JTAG interface sends the programming data
for the serial configuration device to the Cyclone IV device first. The Cyclone IV
device then uses the ASMI pins to send the data to the serial configuration device.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation