EP4CE30F29C7N Datasheet, PDF (322/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–42
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Figure 1–39. Transmitter and Receiver Datapath Clocking with Rate Match FIFO in Bonded Channel Configuration
FPGA
Fabric
Transmitter Channel PCS 3
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 3
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
/2
Transmitter Channel PCS 2
Deskew
FIFO
Word
Aligner
(1)
Transmitter Channel PMA 3
Serializer
high-speed
clock
Receiver Channel PMA 3
Deserial-
izer
CDR
(2)
CDR clock
Transmitter Channel PMA 2
coreclkout
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 2
Serializer
high-speed
clock
Receiver Channel PMA 2
Rx
Phase
Comp
FIFO
/2
Byte
Order-
ing
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
/2
Transmitter Channel PCS 1
Deskew
FIFO
Word
Aligner
(1)
Deserial-
izer
CDR
(2)
CDR clock
Transmitter Channel PMA 1
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 1
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
/2
Transmitter Channel PCS 0
Deskew
FIFO
Word
Aligner
(1)
Serializer
high-speed
clock
low-speed clock
Receiver Channel PMA 1
Deserial-
izer
CDR
(2)
CDR clock
Transmitter Channel PMA 0
Notes to Figure 1–39:
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
Tx Phase
Comp
FIFO
wr_clk rd_clk
Byte Serializer
wr_clk rd_clk
8B/10B Encoder
/2
Receiver Channel PCS 0
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
/2
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
(1)
Serializer
high-speed
clock
Receiver Channel PMA 0
Deserial-
izer
CDR
(2)
CDR clock
In +2 Bonded Channel Configuration
In +4 Bonded Channel Configuration
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation