EP4CE30F29C7N Datasheet, PDF (345/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
1–65
Figure 1–60 shows the transceiver channel datapath and clocking when configured in
Serial RapidIO mode.
Figure 1–60. Transceiver Channel Datapath and Clocking when Configured in Serial RapidIO Mode
FPGA
Fabric
tx_clkout
Notes to Figure 1–60:
(1) Optional rate match FIFO.
(2) High-speed recovered clock.
(3) Low-speed recovered clock.
Tx Phase
Comp
FIFO
wr_clk rd_clk
Transmitter Channel PCS
Byte Serializer
wr_clk rd_clk
/2
8B/10B Encoder
Transmitter Channel PMA
Serializer
high-speed
clock
low-speed clock
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
/2
Receiver Channel PCS
8B/10B
Decoder
Rate
Match
FIFO
(1)
Receiver Channel PMA
Deskew
FIFO
Word
Aligner
(3)
Deserial-
izer
CDR
(2)
CDR clock
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2