EP4CE30F29C7N Datasheet, PDF (364/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–84
Chapter 1: Cyclone IV Transceivers Architecture
Self Test Modes
Table 1–25. PRBS, High and Low Frequency Patterns, and Channel Settings (Part 2 of 2)
8-bit Channel Width
10-bit Channel Width
Patterns
Polynomial
Channel
Width
of
8 bits
(1)
Word
Alignment
Pattern
Maximum
Data Rate
(Gbps) for
F324 and
Smaller
Packages
Maximum
Data Rate
(Gbps) for
F484 and
Larger
Packages
Channel
Width
of
10-bits
(1)
Word
Alignment
Pattern
Maximum
Data Rate
(Gbps) for
F324 and
Smaller
Packages
Maximum
Data Rate
(Gbps) for
F484 and
Larger
Packages
Low
Frequency ⁽²⁾
1111100000
N
—
—
—
Y
—
2.5
3.125
Notes to Table 1–25:
(1) Channel width refers to the What is the channel width? option in the General screen of the ALTGX MegaWizard Plug-In Manager. Based on the
selection, an 8 or 10 bits wide pattern is generated as indicated by a Yes (Y) or No (N).
(2) A verifier and associated rx_bistdone and rx_bisterr signals are not available for the specified patterns.
You can enable the serial loopback option to loop the generated PRBS patterns to the
receiver channel for verifier to check the PRBS patterns. When the PRBS pattern is
received, the rx_bisterr and rx_bistdone signals indicate the status of the verifier.
After the word aligner restores the word boundary, the rx_bistdone signal is driven
high when the verifier receives a complete pattern cycle and remains asserted until it
is reset using the rx_digitalreset port. After the assertion of rx_bistdone, the
rx_bisterr signal is asserted for a minimum of three rx_clkout cycles when errors
are detected in the data and deasserts if the following PRBS sequence contains no
error. You can reset the PRBS pattern generator and verifier by asserting the
tx_digitalreset and rx_digitalreset ports, respectively.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation