EP4CE30F29C7N Datasheet, PDF (397/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 2: Cyclone IV Reset Control and Power Down
Reference Information
2–23
■ In PCIe mode simulation, you must assert the tx_forceelecidle signal for at least
one parallel clock cycle before transmitting normal data for correct simulation
behavior.
Reference Information
For more information about some useful reference terms used in this chapter, refer to
the links listed in Table 2–7.
Table 2–7. Reference Information
Terms Used in this Chapter
Automatic Lock Mode
Bonded channel configuration
busy
Dynamic Reconfiguration Reset Sequences
gxb_powerdown
LTD
LTR
Manual Lock Mode
Non-Bonded channel configuration
PCIe
pll_locked
pll_areset
rx_analogreset
rx_digitalreset
rx_freqlocked
tx_digitalreset
Useful Reference Points
page 2–8
page 2–6
page 2–3
page 2–19
page 2–3
page 2–6
page 2–6
page 2–9
page 2–10
page 2–17
page 2–3
page 2–3
page 2–2
page 2–2
page 2–3
page 2–2
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2