EP4CE30F29C7N Datasheet, PDF (254/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

9–8
Chapter 9: SEU Mitigation in Cyclone IV Devices
Software Support
Figure 9–3 shows the error detection block diagram in FPGA devices and shows the
interface that the WYSIWYG atom enables in your design.
Figure 9–3. Error Detection Block Diagram
80 MHz Internal Chip Oscillator
Clock Divider
(1 to 256 Factor)
Pre-Computed CRC
(Saved in the Option Register)
SRAM
Bits
CRC
Computation
V_CC
Error Detection
Logic
CRC_ERROR
(Shown in BIDIR Mode)
Logic Array
1 The user logic is affected by the soft error failure, so reading out the 32-bit CRC
signature through the regout should not be relied upon to detect a soft error. You
should rely on the CRC_ERROR output signal itself, because this CRC_ERROR output
signal cannot be affected by a soft error.
To enable the cycloneiv_crcblock WYSIWYG atom, you must name the atom for
each Cyclone IV device accordingly.
Example 9–1 shows an example of how to define the input and output ports of a
WYSIWYG atom in a Cyclone IV device.
Example 9–1. Error Detection Block Diagram
cycloneiv_crcblock<crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>),
);
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation