EP4CE30F29C7N Datasheet, PDF (303/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
1–23
Rate Match FIFO
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clocks. Frequency differences in the order of a few
hundred ppm can corrupt the data when latching from the recovered clock domain
(the same clock domain as the upstream transmitter reference clock) to the local
receiver reference clock domain. Figure 1–21 shows the rate match FIFO block
diagram.
Figure 1–21. Rate Match FIFO Block Diagram
10
Rate Match
FIFO
(20-word deep)
10
rx_rmfifodatainserted
rx_rmfifodatadeleted
rx_rmfifofull
rx_fifoempty
The rate match FIFO compensates for small clock frequency differences of up to
±300 ppm (600 ppm total) between the upstream transmitter and the local receiver
clocks by performing the following functions:
■ Insert skip symbols when the local receiver reference clock frequency is greater
than the upstream transmitter reference clock frequency
■ Delete skip symbols when the local receiver reference clock frequency is less than
the upstream transmitter reference clock frequency
The 20-word deep rate match FIFO and logics control insertion and deletion of skip
symbols, depending on the ppm difference. The operation begins after the word
aligner synchronization status (rx_syncstatus) is asserted.
1 Rate match FIFO is only supported with 8B/10B encoded data and the word aligner
in automatic synchronization state machine mode.
8B/10B Decoder
The 8B/10B decoder receives 10-bit data and decodes it into an 8-bit data and a 1-bit
control identifier. The decoder is compliant with Clause 36 of the IEEE 802.3
specification.
Figure 1–22 shows the 8B/10B decoder block diagram.
Figure 1–22. 8B/10B Decoder Block Diagram
10
8B/10B Decoder
8
rx_ctrldetect
rx_errdetect
rx_runningdisp
rx_disperr
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2