EP4CE30F29C7N Datasheet, PDF (319/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
1–39
Figure 1–37. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in F484 and Larger
Packages
+ _{2 Bonded Channel Configuration}
+ _{4 Bonded Channel Configuration}
(1)
MPLL_8
(2)
GPLL_2
(1)
MPLL_8
(2)
Ch3 ^{TX PMA}
TX PMA
Transceiver ^Ch2
Block
TX PMA
GXBL1 ^Ch1
TX PMA
Ch0
(3)
Ch3 ^{TX PMA}
TX PMA
Transceiver ^Ch2
Block
TX PMA
GXBL1 ^Ch1
TX PMA
Ch0
(3)
MPLL_7
MPLL_6
(4)
Not applicable in
F484 package
MPLL_7
MPLL_6
Not applicable in
F484 package
Ch3 ^{TX PMA}
TX PMA
Transceiver ^Ch2
Block
TX PMA
GXBL0 ^Ch1
TX PMA
Ch0
(3)
Ch3 ^{TX PMA}
TX PMA
Transceiver ^Ch2
Block
TX PMA
GXBL0 ^Ch1
TX PMA
Ch0
(3)
MPLL_5
(2)
(1) _{GPLL_1}
(4)
(1)
MPLL_5
(2)
Notes to Figure 1–37:
(1) High-speed clock.
(2) Low-speed clock.
(3) Bonded common low-speed clock path.
(4) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to Table 1–10.
The channel datapath clocking is similar between bonded channels in ×2 and ×4
configurations.
Figure 1–38 shows the datapath clocking in Transmitter Only operation for ×2 and ×4
bonded configurations. In these configurations, each bonded channel selects the
high-speed clock from one the supported PLLs. The high-speed clock in each bonded
channel feeds the respective serializer for parallel to serial operation. The common
bonded low-speed clock feeds to each bonded channel that is used for the following
blocks in each transmitter PCS channel:
■ 8B/10B encoder
■ read clock of byte serializer
■ read clock of TX phase compensation FIFO
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2