EP4CE30F29C7N Datasheet, PDF (336/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Signal Detect at Receiver
In PIPE mode, signal detection is supported with the built-in signal threshold
detection circuitry. When electrical idle inference is not enabled, the rx_signaldetect
signal is inverted and available as pipeelecidle port in the PIPE interface.
Lane Synchronization
In PIPE mode, the word aligner is configured in automatic synchronization state
machine mode that complies with the PCIe specification. Table 1–16 lists the
synchronization state machine parameters that implement the PCIe-compliant
synchronization.
Table 1–16. Synchronization State Machine Parameters ⁽¹⁾
Parameter
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to Table 1–16:
(1) The word aligner supports 10-bit pattern lengths in PIPE mode.
Value
4
17
16
Clock Rate Compensation
In PIPE mode, the rate match FIFO compensates up to ±300 ppm (600 ppm total)
difference between the upstream transmitter and the local receiver reference clock. In
PIPE mode, the rate match FIFO operation is compliant to the version 2.0 of the PCIe
Base Specification. The PCIe protocol requires the receiver to recognize a skip (SKP)
ordered set, and inserts or deletes only one SKP symbol per SKP ordered set received to
prevent the rate match FIFO from overflowing or underflowing. The SKP ordered set
is a /K28.5/ comma (COM) symbol followed by one to five consecutive /K28.0/ SKP
symbols, which are sent by transmitter during the inter-packet gap.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired, as indicated with logic high on
rx_syncstatus signal. Rate match FIFO insertion and deletion events are
communicated to FPGA fabric on the pipestatus[2..0] port from each channel.
Low-Latency Synchronous PCIe
In PIPE mode, the Cyclone IV GX transceiver supports a lower latency in synchronous
PCIe by reducing the latency across the rate match FIFO. In synchronous PCIe, the
system uses a common reference clocking that gives a 0 ppm difference between the
upstream transmitter's and local receiver's reference clock.
f When using common reference clocking, the transceiver supports spread-spectrum
clocking. For more information about the SSC support in PCIe Express (PIPE) mode,
refer to the Cyclone IV Device Data Sheet.
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation