EP4CE30F29C7N Datasheet, PDF (107/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

May 2013
CYIV-51006-2.6
CYIV-51006-2.6
6. I/O Features in Cyclone IV Devices
This chapter describes the I/O and high speed I/O capabilities and features offered in
Cyclone^® IV devices.
The I/O capabilities of Cyclone IV devices are driven by the diversification of I/O
standards in many low-cost applications, and the significant increase in required I/O
performance. Altera’s objective is to create a device that accommodates your key
board design needs with ease and flexibility.
The I/O flexibility of Cyclone IV devices is increased from the previous generation
low-cost FPGAs by allowing all I/O standards to be selected on all I/O banks.
Improvements to on-chip termination (OCT) support and the addition of true
differential buffers have eliminated the need for external resistors in many
applications, such as display system interfaces.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The
Cyclone IV devices support LVDS, BLVDS, RSDS, mini-LVDS, and PPDS. The
transceiver reference clocks and the existing general-purpose I/O (GPIO) clock input
features also support the LVDS I/O standards.
The Quartus^® II software completes the solution with powerful pin planning features
that allow you to plan and optimize I/O system designs even before the design files
are available.
This chapter includes the following sections:
■ “Cyclone IV I/O Elements” on page 6–2
■ “I/O Element Features” on page 6–3
■ “OCT Support” on page 6–6
■ “I/O Standards” on page 6–11
■ “Termination Scheme for I/O Standards” on page 6–13
■ “I/O Banks” on page 6–16
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Cyclone IV Device Handbook,
Volume 1
May 2013
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