EP4CE30F29C7N Datasheet, PDF (429/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
3–31
Option 1: Share a Single Transmitter Core Clock Between Receivers
■ Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the read clock to the Receive Phase Compensation
FIFOs of the remaining receiver channels in the transceiver block.
■ This option is typically enabled when all the channels of a transceiver block are in
a Basic or Protocol configuration with rate matching enabled and are reconfigured
to another Basic or Protocol configuration with rate matching enabled.
Figure 3–13 shows the sharing of channel 0’s tx_clkout between all four channels of a
transceiver block.
Figure 3–13. Option 1 for Receiver Core Clocking (Channel Reconfiguration Mode)
FPGA Fabric
Transceiver Block
TX0
RX0
tx_clkout[0]
TX1
RX1
TX2
MPLL
RX2
TX3
RX3
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
November 2011 Altera Corporation
Cyclone IV Device Handbook,
Volume 2