EP4CE30F29C7N Datasheet, PDF (350/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

1–70
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–64 shows the transceiver configuration in XAUI mode.
Figure 1–64. Transceiver Configuration in XAUI Mode
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Deskew FIFO
Rate Match FIFO
Byte SERDES
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
XAUI
×4
Disabled
Automatic Synchronization
State Machine (7-bit, 10-Bit)
Enabled
Enabled
Enabled
Enabled
3.125
Disabled
16-Bit
156.25
XGMII and PCS Code Conversions
In XAUI mode, the 8B/10B encoder in the transmitter datapath maps various 8-bit
XGMII codes to 10-bit PCS code groups as listed in Table 1–21.
Table 1–21. XGMII Character to PCS Code Groups Mapping (Part 1 of 2)
XGMII TXC ⁽¹⁾
XGMII TXD ^{(2), (3)}
PCS Code Group
0
00 through FF
1
07
1
07
1
9C
1
FB
1
FD
1
FE
Dxx,y
K28.0, K28.3, or K28.5
K28.5
K28.4
K27.7
K29.7
K30.7
Description
Normal data transmission
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation