EP4CE30F29C7N Datasheet, PDF (413/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
3–15
Figure 3–4 shows the write transaction waveform for Method 1.
Figure 3–4. Write Transaction Waveform—Use ‘logical_channel_address port’ Option
reconfig_clk
write_all
rx_tx_duplex_sel [1:0] (1)
2'b00
2'b10
logical_channel_address [1:0] (2)
busy
2'b00
2'b01
tx_vodctrl [2:0]
3'b111
3'b001
Notes to Figure 3–4:
(1) In this waveform example, you are writing to only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
logical_channel_address port is 2 bits wide.
Read Transaction
For example, to read the existing V_OD values from the transmit V_OD control registers of
the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG
instance, perform the following steps:
1. Set the logical_channel_address input port to the logical channel address of the
transceiver channel whose PMA controls you want to read (for example,
tx_vodctrl_out).
2. Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are
read from the transceiver channel.
3. Ensure that the busy signal is low before you start a read transaction.
4. Assert the read signal for one reconfig_clk clock cycle. This initiates the read
transaction.
The busy output status signal is asserted high to indicate that the dynamic
reconfiguration controller is busy reading the PMA control values. When the read
transaction has completed, the busy signal goes low. The data_valid signal is asserted
to indicate that the data available at the read control signal is valid.
November 2011 Altera Corporation
Cyclone IV Device Handbook,
Volume 2