EP4CE30F29C7N Datasheet, PDF (159/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Features
7–13
Figure 7–7 illustrates Cyclone IV DDR input registers.
Figure 7–7. Cyclone IV DDR Input Registers
DDR Input Registers in Cyclone IV Device
dataout_h
dataout_l
LE
Register
Register C_I
LE
Register
Input Register A_I
neg_reg_out
LE
Register
Input Register B_I
DQ
Capture Clock
PLL
These DDR input registers are implemented in the core of devices. The DDR data is
first fed to two registers, input register A_I and input register B_I.
■ Input register A_I captures the DDR data present during the rising edge of the clock
■ Input register B_I captures the DDR data present during the falling edge of the clock
■ Register C_I aligns the data before it is synchronized with the system clock
The data from the DDR input register is fed to two registers, sync_reg_h and
sync_reg_l, then the data is typically transferred to a FIFO block to synchronize the
two data streams to the rising edge of the system clock. Because the read-capture
clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used
during read operation in Cyclone IV devices; hence, postamble is not a concern in this
case.
May 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 1