EP4CE30F29C7N Datasheet, PDF (351/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
1–71
Table 1–21. XGMII Character to PCS Code Groups Mapping (Part 2 of 2)
XGMII TXC ⁽¹⁾
XGMII TXD ^{(2), (3)}
PCS Code Group
1
Any other value
K30.7
Notes to Table 1–21:
(1) Equivalent to tx_ctrlenable port.
(2) Equivalent to 8-bit input data to 8B/10B encoder.
(3) The values in XGMII TXD column are in hexadecimal.
Description
Invalid XGMII character
8B/10B decoder in the receiver datapath maps received PCS code groups into specific
8-bit XGMII codes as listed in Table 1–22.
Table 1–22. PCS Code Groups to XGMII Character Mapping
XGMII RXC ⁽¹⁾
XGMII RXD ^{(2), (3)}
PCS Code Group
0
00 through FF
1
07
1
07
1
9C
1
FB
1
FD
1
FE
1
FE
Dxx,y
K28.0, K28.3, or K28.5
K28.5
K28.4
K27.7
K29.7
K30.7
Invalid code group
Notes to Table 1–22:
(1) Equivalent to rx_ctrlenable port.
(2) Equivalent to 8-bit input data to 8B/10B encoder.
(3) The values in XGMII RXD column are in hexadecimal.
Description
Normal data transmission
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Received code group
Channel Deskewing
The deskew FIFO in each of the four lanes expects to receive /A/ code group
simultaneously on all four channels during the inter-packet gap, as required by XAUI
protocol. The skew introduced in the physical medium and the receiver channels
might cause the /A/ code group to be received misaligned with respect to each other.
The deskew FIFO works to align the /A/ code group across the four channels, which
operation is compliant to the PCS deskew state machine diagram specified in
clause 48 of the IEEE P802.3ae specification. The deskew operation begins after link
synchronization is achieved on all four channels as indicated by the word aligner in
each channel. The following are the deskew FIFO operations:
■ Until the first /A/ code group is received, the deskew FIFO read and write
pointers in each channel are not incremented.
■ After the first /A/ code group is received, the write pointer starts incrementing for
each word received but the read pointer is frozen.
■ When all the four channels received the /A/ code group within 10 recovered clock
cycles of each other, the read pointer of all four deskew FIFOs is released
simultaneously, aligning the /A/ code group of all four channels in a column.
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2