EP4CE30F29C7N Datasheet, PDF (301/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
1–21
■ Receiver polarity inversion—corrects accidental swapped positive and negative
signals from the serial differential link during board layout. This feature works by
inverting the polarity of every bit of the input data word to the word aligner,
which has the same effect as swapping the positive and negative signals of the
differential link. Inversion is dynamically controlled using rx_invpolarity port.
Figure 1–19 shows the receiver polarity inversion feature.
Figure 1–19. Receiver Polarity Inversion
Output from deserializer
Input to word aligner
0 MSB
1
1
1
rx_invpolarity = HIGH
0
0
0
1
0
0 LSB
1 MSB
0
0
0
1
1
1
0
1
1 LSB
The generic receiver polarity inversion feature is different from the PCI Express (PIPE)
8B/10B polarity inversion feature. The generic receiver polarity inversion feature
inverts the polarity of the data bits at the input of the word aligner and is not available
in PCI Express (PIPE) mode. The PCI Express (PIPE) 8B/10B polarity inversion
feature inverts the polarity of the data bits at the input of the 8B/10B decoder and is
available only in PCI Express (PIPE) mode.
1 The rx_invpolarity signal is dynamic and might cause initial disparity errors in an
8B/10B encoded link. The downstream system must be able to tolerate these disparity
errors.
■ Receiver bit reversal—by default, the Cyclone IV GX receiver assumes LSB to MSB
transmission. If the link transmission order is MSB to LSB, the receiver forwards
the incorrect reverse bit-ordered version of the parallel data to the FPGA fabric on
the rx_dataout port. The receiver bit reversal feature is available to correct this
situation. This feature is static in manual alignment and automatic
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2