EP4CE30F29C7N Datasheet, PDF (382/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

2–8
Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. When the
receiver CDR is in automatic lock mode, use the reset sequence shown in Figure 2–4.
Figure 2–4. Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels—Receiver CDR in
Automatic Lock Mode
Reset Signals
1 μs
1
2
pll_areset
4
tx_digitalreset
rx_analogreset
6
8
rx_digitalreset
Output Status Signals
pll_locked
busy (3)
rx_freqlocked[0]
3
Two parallel clock cycles
5
7
7
rx_freqlocked[n] (1)
tLTD_Auto (2)
Notes to Figure 2–4:
(1) The number of rx_freqlocked[n] signals depend on the number of channels configured. n=number of channels.
(2) For t_{LTD_Auto} duration, refer to the Cyclone IV Device Datasheet chapter.
(3) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the busy
signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
As shown in Figure 2–4, perform the following reset procedure for the receiver CDR
in automatic lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
between markers 1 and 2).
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
asserted during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the input reference clock.
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
high, deassert the tx_digitalreset signal. At this point, the transmitter is ready
for data traffic.
Cyclone IV Device Handbook,
Volume 2
May 2013 Altera Corporation