EP4CE30F29C7N Datasheet, PDF (332/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Receiver Spread Spectrum Clocking
Asynchronous SSC is not supported in Cyclone IV devices. You can implement only
synchronous SSC for SATA, V-by-One, and Display Port protocols in Basic mode.
PCI Express (PIPE) Mode
PIPE mode provides the transceiver channel datapath configuration that supports ×1,
×2, and ×4 initial lane width for PCIe Gen1 signaling rate with PIPE interface
implementation. The Cyclone IV GX transceiver provides following features in PIPE
mode:
■ PIPE interface
■ receiver detection circuitry
■ electrical idle control
■ signal detect at receiver
■ lane synchronization with compliant state machine
■ clock rate compensation with rate match FIFO
■ Low-Latency Synchronous PCIe
■ fast recovery from P0s state
■ electrical idle inference
■ compliance pattern transmission
■ reset requirement
Figure 1–48 shows the transceiver channel datapath and clocking when configured in
PIPE mode with ×1 channel configuration.
.
Figure 1–48. Transceiver Channel Datapath and Clocking when Configured in PIPE Mode with ×1 Channel Configuration
FPGA
Fabric
Tx Phase
Comp
FIFO
wr_clk rd_clk
Transmitter Channel PCS
Byte Serializer
wr_clk rd_clk
/2
8B/10B Encoder
Transmitter Channel PMA
Serializer
high-speed
clock
low-speed clock
Notes to Figure 1–48:
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
Rx
Phase
Comp
FIFO
Byte
Order-
ing
Byte
De-
serializer
/2
Receiver Channel PCS
8B/10B
Decoder
Rate
Match
FIFO
Receiver Channel PMA
Deskew
FIFO
Word
Aligner
(1)
Deserial-
izer
CDR
CDR clock
(2)
Cyclone IV Device Handbook,
Volume 2
October 2013 Altera Corporation