EP4CE30F29C7N Datasheet, PDF (194/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–30
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–11 shows the recommended balanced star routing for multiple bus master
interfaces to minimize signal integrity issues.
Figure 8–11. Balanced Star Routing
DCLK
Cyclone IV E
Master Device
M (1)
External
Master Device
N (2)
N (2)
Micron Flash
Notes to Figure 8–11:
(1) Altera recommends that M does not exceed 6 inches, as listed in Table 8–11 on page 8–28.
(2) Altera recommends using a balanced star routing. Keep the N length equal and as short as possible to minimize
reflection noise from the transmission line. The M length is applicable for this setup.
Estimating AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to Cyclone IV E devices. This parallel interface is clocked by the
Cyclone IV E DCLK output (generated from an internal oscillator). The DCLK minimum
frequency when using the 40-MHz oscillator is 20 MHz (50 ns). In word-wide cascade
programming, the DATA[15..0] bus transfers a 16-bit word and essentially cuts
configuration time to approximately 1/16 of the AS configuration time. Equation 8–4
and Equation 8–5 show the configuration time calculations.
Equation 8–4.
Size
×


m_---1--6-a_---x_-b--i_-im--t--s--u_--p-m_---e--r--D_--D---C_--C--L_--L--K_--K----p_--c-e_-y--r_--c-i_-lo--e--d_{--}
=
estimated maximum configuration time
Equation 8–5.
9,600,000
bits
×


1^-5---60^----bn^---i^-s-t^{-}
=
30 ms
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation